1. Field of the Invention
The present invention relates to photolithography techniques and photolithographic masks and methods for fabricating such masks.
2. Description of Related Art
Dimensions of integrated circuits continue to become smaller in order to fit more circuitry in a given area. Multilayer integrated circuits have had the width of the electrically conductive layers in a set of parallel electrically conductive layers, as well as the width of the dielectric layers separating the electrically conductive layers, reduced. However, the lateral dimensions or diameters for the interlayer connectors, including plugs and vias, which contact the individual electrically conductive layers, is often large enough so that the possibility of a single interlayer connector contacting two adjacent electrically conductive layers has become a problem. While various schemes have been devised in response to this issue, none are ideal for all circumstances. See, for example, the following co-pending U.S. patent application Ser. No. 13/049,303, filed 16 Mar. 2011, entitled REDUCED NUMBER OF MASK FOR IC DEVICE WITH STACKED CONTACT LEVELS; and Ser. No. 13/114,931, filed 24 May 2011, entitled MULTILAYER CONNECTION STRUCTURE AND MAKING METHOD, now U.S. Pat. No. 8,383,512.